The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device and a decoder therein to reduce the number of transistors that make up the decoder, and to reduce the layout area of the decoder positioned between memory cell blocks.
In general, the semiconductor memory device is constructed to store data at memory cell arrays made up of a plurality of memory cells. In order to select one out of a plurality of memory cells, a block row decoder decodes a row address to pick one out of a plurality of word lines and a column decoder decodes a column address to select one out of a plurality of bit lines corresponding with the selected memory cell.
The decoder of a conventional semiconductor memory device uses NAND gates and inverters to decode addresses. If the capacity of the semiconductor memory device increases, the number of addresses also increases, further increasing the number of NAND gates and inverters that make up the decoder.
Particularly, a block row decoder of the conventional semiconductor memory device is positioned between blocks of memory cell arrays. As the number of memory cells (and thus word lines) increases, the number of transistors that make up the block row decoder also increases.
The conventional block row decoder is made up of a NAND gate and an inverter to perform an AND operation with a block control signal and a global word line signal, to thereby output a local word line signal.
Particularly, as the integration degree of memory cell array blocks increases, the space or interval between blocks of the memory cell arrays is reduced. As the number of word lines increases, it gets more and more difficult to realize memory cell arrays.
In consequence, there is a problem in the conventional decoder of the semiconductor memory device in that the structure of the decoder gets complicated to bring about difficulty in layout of memory cell array blocks with a narrow interval therebetween.
FIG. 1 is a block diagram for illustrating arrangement of a conventional memory device, including n memory cell array blocks MCAB1, MCAB2, . . . , MCABn, a global row decoder GRD and n block row decoders BRD1, BRD2, . . . , BRDn positioned between n memory cell array blocks.
The global row decoder GRD inputs i row addresses Ai to generate k global word line signals GWL1, GWL2, GWL3,. . . , GWLk. The n block row decoders respectively respond to block control signals B1, B2,. . . Bn to convert the global word line signals into local word line signals LWL1, LWL2, . . . , LWLk which are, then, transmitted to memory cell array blocks MCA1, MCA2, . . . , MCABn.
FIG. 2 is a block diagram for illustrating an embodiment of a block row decoder of a conventional semiconductor memory device, which shows the structure of the row address decoder in case that four addresses XA1, XA2, XA3, XA4 are inputted from outside the memory device.
The decoder shown in FIG. 2 includes buffers 10-1, 10-2, 10-3, 10-4, global row decoders GRD having pre-decoders PRD1, PRD2 and a main decoder DE, and a block row decoder BRD.
The buffers 10-1, 10-2, 10-3, 10-4 respectively buffer the addresses XA1, XA2, XA3, XA4 inputted from outside of the semiconductor memory device to respectively generate buffered addresses (A1, A1B), (A2, A2B), (A3, A3B), (A4, A4B). The pre-decoder PRD1 decodes the signals inputted from the buffers 10-1, 10-2 to generate decoded output signals d1, d2, d3, d4. The pre-decoder PRD2 decodes the signals inputted from the buffers 10-3, 10-4 to generate decoded output signals d5, d6, d7, d8. The decoder DE inputs the output signals d1, d2, d3, d4, d5, d6, d7, d8 of the pre-decoders PRD1, PRD2 to generate global word line signals GWL1, GWL2, . . . , GWL16. The block row decoder BRD responds to a block control signal Bn to respectively convert global word line signals GWL1, GWL2, . . . , GWL16 into local word line signals LWL1, LWL2, . . . , LWL16.
FIG. 3 is a circuit diagram for illustrating an embodiment of the global row decoder GRD and the block row decoder BRD of the block diagram shown in FIG. 2. The pre-decoder PRD1 is constructed with decoding cells 20-1, 20-2, 20-3, 20-4 having NAND gates NA and inverters I for respectively ANDing pairs of buffered addresses (A1B, A2B), (A1B, A2), (A1, A2B), (A1, A2) to respectively generate output signals d1, d2, d3, d4. The pre-decoder PRD2 is constructed with decoding cells 20-5, 20-6, 20-7, 20-8 having NAND gates NA and inverters I for respectively ANDing pairs of buffered addresses (A3B, A4B), (A3B, A4), (A3, A4B), (A3, A4) to respectively generate output signals d5, d6, d7, d8.
The main decoder DE includes decoding cells 30-1, 30-2, 30-3, 30-4, . . . , 30-13, 30-14, 30-15, 30-16 having NAND gates and inverters I for respectively ANDing pairs of decoded output signals (d1, d5), (d1, d6), (d1, d7), (d1, d8),. . . , (d4, d5), (d4, d6), (d4, d7 pre-decoders PRD1, PRD2 to respectively generate 16 global word line signals GWL1, GWL2, GWL3, GWL4, . . . , GWL13, GWL14, GWL15, GWL16. The block row decoder BRD is constructed with decoding cells 40-1, 40-2,. . . , 40-16 having NAND gates NA and inverters I for respectively ANDing the global word line signals GWL1, GWL2, . . . , GWL16 outputted from the main decoder DE with the block control signal Bn to respectively generate 16 local word line signals LWL1, LWL2, . . . , LWL16.
The decoder described above performs operations in the following Table.
TABLE G G G G G G G G G G G G G G G G W W W W W W W W W W W W W W W W L L L L L L L A A A A d d d d d d d d L L L L L L L L L 1 1 1 1 1 1 1 1 2 3 4 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
The decoder of the conventional semiconductor memory device thus constructed increases the number of addresses in accordance with increasing the capacity of memory cell arrays, thereby increasing the number of transistors that make up the decoder.
However, there is a problem in the decoder of the conventional semiconductor memory device in that the increase in the number of the transistors of the row block decoder formed between the blocks of the memory cell arrays reduces layout efficiency and increases the surface area of the chip.
Thus, in order to solve the aforementioned problem of the prior art, a technique is disclosed in U.S. Pat. No. 5,808,500, wherein the block row decoder positioned between blocks of memory cell arrays is constructed with transmission gates to transmit global word line signals to local word lines in response to the block control signals and a clamp circuit to put the local word lines into their inactive states in response to the block control signals. In other words, the number of transistors that make up the block row decoder is reduced for a more efficient layout.
The technique disclosed in U.S. Pat. No. 5, 808,500 has been successful in modestly reducing the number of transistors that make up the block row decoder. However, there is still a problem in the aforementioned technique in that the number of transistors that make up the global row decoder could not be reduced. Consequently, the disclosed technique failed to significantly reduce the number of total transistors that make up the overall decoder requirements in a semiconductor memory device.